PaulELong t first I assumed SPI0 = /dev/SPI1. and SPI1 = /dev/SPI2.,
that is correct, according to the reference you found, and it would be the same on BElaMini.
PaulELong I saw on some other Linux versions that you can use some kernel configuration to hardware enable SPI.
No. that is already enabled.
So, I ran your code (this commit: 05571b259976a493fb7a9392ea028d6c52a7cbc0) on the board and hooked up pins P2.25, P2.27, P2.29, P2.31 to scope.
What I see is that:
- each transmission transmits 8bits
- the bit clock rate is effectively 24MHz
- between the CS line going down and the start of the transmission there are about 3-4us
- between the end of the transmission and the CS line going up there are about 1.4us
- in between transmissions, the CS line stays high for about 37us
(the above are typical values, but things get worse in some cases, e.g.: when the thread is preempted)
So, ultimately, the bottleneck is not in the clock speed of the transmission itself, but mostly the dead time before and after the transmission.
There are ways this could be improved by packing multiple bytes in a single transmission, or in a single ioctl()
(see e.g. the DEV_HARDWARE_SPI_Transfer()
function in dev_hardware_SPI.c
), but how this can be done depends on the characteristics of the device: can it use larger words (e.g.: 32bit)? can it receive several words within a single chip-select cycle?
See more details on what parameters to pass to the ioctl
here.
I am a bit surprised by the large overhead that comes with each transfer, but I cannot see where the device could be configured to perform better, and in fact I tried the library I linked above and it performs exactly the same : in a tight loop it takes about 40us per each 8-bit transaction.