Hey,

this seems a pretty basic question, but I can't figure this out:

The clock speed on /dev/i2c-1 apparently defaults to 100KHz. How can I change it?

I think the only way to do it is change the value in the device tree overlay:

  • edit the file /opt/bb.org-overlays/src/arm/BB-BELA-00A1.dts: there is a block of text that goes: 
            fragment@3 {
                target = <&i2c1>;
                __overlay__ {
                        pinctrl-names = "default";
                        pinctrl-0 = <&i2c1_pins>;

                        status = "okay";
                        clock-frequency = <100000>;
                };
        };
    replace the clock-frequency with another supported value (not sure what the values are, but I am fairly sure 400000 is the highest you can get).
    • recompile and install: make -C /opt/bb.org-overlays/ && make -C /opt/bb.org-overlays/ install
    • reboot
    • let us know if this works fine, we can probably make this the new default.

Oh cool! I changed it to 1000000, and so far, it's working perfectly fine for me. I'm talking to an ESP32 slave. Thanks!

Having no experience with device trees, I found this pretty obscure -- at first I thought there would be some ioctl or similar. Not sure what the most sensible default value would be, but maybe this information would be good to have in the wiki?

Fair point, although in principle we'd like to avoid having to duplicate information that is more generically applicable to Linux/embedded Linux/Beaglebone , and not necessarily Bela-specific, because in order to be exhaustive, this would become a massive undertake.

and the wiki is open for contributions to all github users! 😉

The technical reference manual for the chip says

The general features of the I2C controller are:
• Compliant with Philips I2C specification version 2.1
• Supports standard mode (up to 100K bits/s) and fast mode (up to 400K bits/s).
• Multimaster transmitter/slave receiver mode
• Multimaster receiver/slave transmitter mode
• Combined master transmit/receive and receive/transmit modes
• 7-bit and 10-bit device addressing modes
• Built-in 32-byte FIFO for buffered read or writes in each module
• Programmable clock generation
• Two DMA channels, one interrupt line

So, 400000 should be the maximum allowed value. Can you scope the SCL line and see what the clock frequency actually is?

    giuliomoro So, 400000 should be the maximum allowed value. Can you scope the SCL line and see what the clock frequency actually is?

    probably easier than that, check in dmesg or somewhere in /sys/ what the actual frequency is. I tried to look for it in /sys, but to no avail.

      dmesg | grep -i i2c shows
      [ 1.027247] omap_i2c 4802a000.i2c: bus 1 rev0.11 at 1000 kHz

      My test program shows a net rate of around 100000 bytes per second, which seems roughly right. According to my scope, the clock frequency is 909 KHz. The difference could be some kind of rounding error, or granularity in timing? (Ie, exactly 1000 KHz might be impossible to configure with this hardware, and 909KHz is closest.)

      The AM335x Technical Reference Manual seems a bit vague. It says 100 KHz and 400 KHz are supported, but nothing explicit about the maximum clock speed. It does say
      "High Speed (3.4 MBPS) operation Not supported"

      The I2C spec contains "standard mode" (100KHz), "fast mode" (400KHz) and "High-speed mode" (with "up to" 3.4 Mbit/s). Maybe the AM335x controller can't go quite as fast, and technically there's no name for a mode with a ~1MHz clock, so that's why they don't mention it.

      In any case, I left the transfers running for a couple hours now and everything seems stable.