AndyCap So is the issue the func_24m_clk being wrong?
Yes, if you were to scope P9.25, you would see 20MHz instead of 24MHz. This is strange, because - afaik from the Technical Reference Manual - that clock (called FUNC_24M_GFCLK
in the TRM) is not programmable (hence the 24M
in the name ), and has a fixed divide down by 4 from FUNC_96M_AON_CLK
(96MHz) (see Figure 3-44. CM_CORE_AON Overview (a)
), generated by DPLL_PER
(see Figure 3-56. DPLL_PER Overview
). So the problem is either in the programming of the DPLL_PER
itself or in the frequency of its input, that is SYS_CLK1
(see Figure 3-43. PRM Clock Manager Overview
), which is in turn generated by OSC0
(see Figure 3-19. PMFW Overview
).
Now, what is OSC0? 3.6.2.2
says
The system clocks SYS_CLK1 and SYS_CLK2, are the main source clocks of the device. SYS_CLK1 and SYS_CLK2 are received directly from internal oscillators (OSC0 and OSC1) of the PRCM module.
However Table 3-23
says:
System Oscillator OSC0 Crystal Input.This is the main system clock of the device.
So it seems a bit confusing whether the oscillator is actually internal or external. The schematics show a crystal there, so I guess it is external after all. I am searching in the device tree where the frequency of sys_clkin1
is declared, but all I can find is (in dra7xx-clocks.dtsi
):
&prm_clocks {
sys_clkin1: sys_clkin1@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
};
...
}
So things to be tried are:
- see if we can prob the oscillator frequency on the board (although I assume that this will in turn affect the clock's frequency)
- try tweaking the device tree a bit to declare the clock to be 20MHz
- assuming there is an issue with sys_clkin1
, try and use a different clock source (coming from sys_clkin2
)
Note: in the process of the investigation I also found that abe_24m_fclk
is 32MHz instead of 24MHz.