- Edited
Due to size constraints I'm designing a custom PCB with audio codec to use with Bela software. My design requirements are 8 balanced output channels and at least 2 input channels.
I was thinking of using a Cirrus Logic CS42448 as it is readily available at Mouser (2000+ in stock), I have a few already here at home, it has differential DAC outputs and I've used this part before paired with a STM32 (in TDM follower/slave mode, clock generated by STM32 PLL). The CS42448 has no PLL clock generator so I would need to include a crystal on the PCB myself right? I noticed that both the Bela itself and the CTAG cape use a codec with built-in PLL? Why? Can the Beaglebone not generate a quality clock?
The thought crossed my mind to use the AD1938 instead as that codec is already implemented in the Bela core. I found that it only has single ended outputs and found then the AD1939 which looks like it's exactly the same but has differential outputs and thus a larger package. Both the AD1939 and AD1939 are out of stock at Mouser and I can't find application notes on recommended buffers for balanced I/O (which I was able to find for Cirrus Logic codecs..).
Anything I should keep in mind if I'm going to design a board around the CS42448?
- include a 12.288 MHz crystal (Fs * 256) on the board.
- write an I2C (or SPI) startup routine to configure the codec before audio starts.
- configure the codec to use a bit depth of 16 bit
I was also wondering. The audio I/O being 16 bit on the Bela, does that have to do with PRU <--> application communication or hardware limitations?